This invention relates generally to a method of producing a semiconductor device, and more particularly to a flattening technique used in a method of producing a semiconductor memory device and a dynamic random access memory (DRAM).
In recent years, there has been an increasing in the degree of a memory node in a stack-type RAM with its finer and more highly-integrated design in order to fix a charge storage capacity.
One example of conventional methods of producing such a semiconductor device (particularly a semiconductor memory device) will now be described with reference to the drawings.
FIGS. 11A to 11D, 12A to 12C and 13a to 13b show a technique of forming a conventional semiconductor memory device.
As shown in FIG. 11A, word lines 24 are first formed. Then, as shown in FIG. 11B, after a silicon oxide film 25 is deposited, bit lines 26 are formed, and a silicon oxide film 27 is further formed. Then, as shown in FIG. 11C, a contact window 28 is formed by an anisotropic etching in such a manner that it reaches an n+active region of a switching transistor formed on a p-type silicon substrate 23. Then, a first polycrystalline silicon 29 containing impurities is deposited, and then a first resist pattern 30 is formed on this silicon 29. Then, as shown in FIG. 11D, using the first resist pattern 30 as a mask, the first polycrystalline silicon 29 containing the impurities is subjected by RIE to an anisotropic etching to form a memory node pattern 31. Then, as shown in FIG. 12A, a dielectric film 32, composed of a silicon oxide film and a silicon nitride film, is formed on the surface of the memory node pattern 31, and a second polycrystalline silicon 33 containing impurities is deposited through this dielectric film 32, and a second resist pattern 34 is formed on this second polycrystalline silicon 33. Then, as shown in FIG. 12B, using this second resist pattern 34 as a mask, the second polycrystalline silicon film 33 containing the impurities is etched to form a cell plate electrode pattern 36. Then, as shown in FIG. 12C, a BPSG film 40 is deposited on the entire surface of the cell plate electrode pattern 36. Then, as shown in FIG. 13A, the BPSG film 40 is caused to viscously flow by a heat treatment. Finally, as shown in FIG. 13B, an aluminum wiring 45 is formed on the BPSG film 40.
Features of the above-mentioned method of producing a semiconductor memory device will now be described.
First, in the stack-type DRAM, in order to form a charge storage portion, the cell plate electrode pattern is designed with an overlapping dimension 35 in view of a mask misalignment from the memory node pattern (see, for example, Japanese Patent Publication No. 61-55258). Generally, with respect to this overlapping dimension, the mask misalignment dimension is about 0.15 .mu.m when an optical reduction exposure device is used, and a step on the substrate for the BPSG film in a boundary region between a memory cell array portion and a peripheral circuit portion, or in a word line-backing contact forming region, is produced mainly by the memory node and the cell plate electrode. If the height of the memory node is small, the inclination angle (flow angle 44) of the surface of the BPSG film is made small by a viscous flow of the BPSG film, and the step is made sufficiently gentle not to lower the wiring yield.
However, in the above construction, with a more highly-integrated design of the semiconductor memory device, in order to prevent a short channel effect of the switching transistor, the heat treatment for causing the viscous flow of the BPSG film must be carried out at low temperatures in a short time, so that the smoothing of the step becomes difficult. Further, with the highly-integrated design, in order to fix the charge storage capacity, the polycrystalline silicon film for the memory node must be increased in thickness, and the step in the boundary region between the memory cell array portion and the peripheral circuit portion, as well as the step in the memory cell word line-backing contact forming region, becomes excessive, and the viscous flow of the BPSG film under the conventional conditions can not make the step sufficiently smooth and gentle. As a result, the aluminum wiring is cut in the boundary region, and an etching residue for the embedded electrode (made, for example, of tungsten) for forming the word line-backing contact remains, and this has resulted in a problem that the yield of the aluminum wiring is adversely affected.
Methods which are thought to enhance the smoothing of the step by the viscous flow of the BPSG film are (1) to reduce the step on the substrate for the BPSG film, (2) to increase the thickness of the BPSG film, (3) to increase the concentration of impurities in the BPSG film, and (4) to carry out the heat treatment of the BPSG film at high temperatures for a long time.
In one conventional technique which uses the method (1) of reducing such a step in the boundary region between the memory cell array portion and the peripheral circuit portion, only the memory cell forming region is selectively oxidized before the memory cell portion is formed, and then the oxide film is removed to beforehand make the memory cell forming region lower than the peripheral circuit forming region (For example, K. Sagara et al., 1992 Symposium on VLSI Technology, Digest of Technical Papers, pp. 10-11).
If the thickness of the BPSG film is increased using the method (2), it becomes difficult to form the embedded electrode when forming the contact by etching the BPSG film. When the impurity concentration is made excessive using the method (3), deposits develop on the surface of the BPSG film. When the heat treatment is carried out at high temperatures for a long time, using the method (4), the depth of the diffusion layer of the switching transistor increases to cause a short channel effect. Therefore, any of the above methods is not desirable.